Technology for transmitting and receiving data divided into frames is widely used in the field of cable and wireless communications. In the frames used, a preamble (PR) and a unique word (UW) are prefixed ahead of data of a predetermined length. FIG. 2 shows a frame structure. The PR is provided at the head of the frame. The receiver performs gain control, frequency synchronization, symbol synchronization and the like during reception of the PR, in order to control the state in which the UW and data portions following the PR are received. Here, symbol synchronization is processing at the receiver to recover the timing (i.e. symbol clock) of the decision point at which the eye pattern of a symbol is most open, the symbol clock being generated by a clock recovery circuit.
In a typical method for clock recovery, the temporal position of zero crossings on both the in-phase (I) and quadrature (Q) axes are detected and used to recover the symbol clock. FIG. 3 schematically shows clock adjustment in a clock recovery circuit. In the clock recovery shown in FIG. 3, a phase error E with phase error information obtained from an input signal is detected based on a recovered symbol clock, and the clock phase is adjusted so as to reduce the phase error. Here, zero-crossing signals are used to adjust the clock phase in recovering the symbol clock, and thus referred to as phase error information. While fast phase locking is achieved when phase error information occurs successively within the symbol cycle because of the phase error being the same, phase locking is slowed when the phase error information occurs out of the symbol cycle due to the effects of jitter. An alternating pattern in which the phase of adjacent symbols inverts 180° is thus used in the PR, and the receiver obtains received data by generating a symbol clock using phase error information obtained successively from the alternating pattern and acquiring the decision point timing of the symbols based on the generated symbol clock.
Frequency shifts, phase noise and the like in the local oscillators of both the transmitter and the receiver cause phase shifts to occur between signals transmitted by the transmitter and signals received by the receiver. Frequency synchronization is thus required at the receiver, this processing being performed by a phase error correction (PEC) circuit for correcting phase shifts in received signals, or an automatic frequency control (AFC) circuit for directly controlling the oscillation frequency of the local oscillator in the receiver.
FIG. 4 shows the structure of a receiver. A PEC circuit 402 corrects phase errors in a detected signal input 411 from a signal detection unit 401, a clock recovery circuit 1 uses a phase-corrected signal 412 to generate a symbol clock 128, and a data decision unit 403 performs a data decision on phase-corrected signal 412 using symbol clock 128 to obtain received data 413. Note that symbol clock 128 is also used in PEC circuit 402 to calculate a phase correction value.
Normally, as shown in FIG. 4, correct received data can be obtained by performing the frequency synchronization (here, phase error correction) upstream of the symbol synchronization (here, symbol clock recovery). However, when frequency shift causes a large phase shift in the received signal, the cyclicity of the zero-crossing signals is disrupted. The phase error information thus becomes indeterminate due to multiple eyes opening in the symbol period when there should only be one eye, making clock recovery difficult. This is because the clock recovery circuit tries to lock the clock phase to the pseudo eyes. Also, errors occur in the phase correction performed at the PEC circuit based on the symbol clock generated by the clock recovery circuit, resulting in errors in the received data. Note that in the following description, phase shift in the detected signal caused by frequency shift is a different parameter to phase errors in the symbol clock being recovered.
In a conventional clock recovery technique using zero-crossing signals as phase error information, as shown in Japanese Patent Application Publication No. 2001-35095, only valid phase error signals are selected.
FIG. 37 is a block diagram showing the structure of an error selection circuit included in a clock recovery circuit recited in the above art. In the error selection circuit shown in FIG. 37, a T counter circuit 3700 measures the time interval between zero point information showing zero crossings, and an error-selection control signal generator 3701 judges whether the T count is within a predetermined range and outputs an error selection control signal based on the judgment result. An AND circuit 3704 evaluates both the current error selection control signal and the preceding error selection control signal stored at a D flip-flop circuit 3703, and outputs an error selection control signal 3710 based on the evaluation result to switching circuit 3706.
When the time intervals between the current zero crossings and the preceding zero crossings are both bit clock time periods that fall within a range defined by minimum and maximum values, the conventional error selection circuit outputs the phase error signal from a phase detector, having judged the phase error signal to show a substantially accurate phase error. On the other hand, if either one of these time intervals falls outside the set range, the conventional error selection circuit invalidates the phase error signal from the phase detector, having judged the phase error signal to be of doubtful accuracy.
The prior art is thus able to avoid causing phase fluctuation, bit slip and the like and thereby stabilize phase tracking performance, by validating only phase error signals relating to inversion intervals within the set range, and invalidating both phase error signals occurring immediately after short inversion intervals having a low signal level and phase error signals occurring immediately before and after long inversion intervals during which phase errors accumulate, due to the low reliability of phase errors in both cases.
In the field of cable and wireless communications targeted by the present invention, the following problems arise when a conventional error selection circuit applied in relation to binary digital signals in a digital signal player that plays information recorded on recording media such as DVD (digital versatile disc) performs symbol synchronization at the head of the frame with frequency shift in the received signal, during burst transmission using modulated signals in frame format.
Consider an example in which signals are modulated using π/4 DQPSK (Differential Quadrature Phase Shift Keying) Normally, an alternating pattern “10 01” is used in the PR sequence, and the clock recovery circuit uses a cyclic signal inherent in this sequential pattern as phase error information to recover the symbol clock. Note that FIG. 5 shows the phase transition amount for two bits (Xn, Xn+1) per symbol.
FIG. 6 shows the transition of a detected π/4 DQPSK signal when the alternating pattern. A signal point A in the −π/4 phase transits alternately with a signal point B in the 3π/4 phase. Here, the transition AB from point A to point B and the transition BA from point B to point A always transit in the same direction relative to the alternating axis. This transition is referred to here as an arc-shaped transition. The reason for this arc-shaped transition is as follows.
FIG. 7 shows the transition of a predetection π/4 DQPSK signal when the alternating pattern. The intermediate points (Man, Mbn, where n=1, 2, 3, 4) of the signal transition shown in FIG. 8 are expressed asMa1: ma·exp(π/8), Mb1: mb·exp(3π/8)Ma2: ma·exp(5π/8), Mb2: mb·exp(7π/8)Ma3: ma·exp(9π/8), Mb3: mb·exp(11π/8)Ma4: ma·exp(13π/8), Mb4: mb·exp(15π/8).Therefore, the differential detection output at adjacent intermediate points (Ma1 & Mb1, Mb1 & Ma2, Ma2 & Mb2, Mb2 & Ma3, Ma3 & Mb3, Mb3 & Ma4, Ma4 & Mb4, Mb4 & Ma1) for all combinations can be expressed asmamb·exp(π/4).  (1)Expression 1 indicates that the transition of the differentially detected signal always has a component in a π/4 phase direction between two signal points. That is, the signal transits in the same direction relative to the alternating axis. Thus with π/4 DQPSK modulation, the transition of the differentially detected signal is arc-shaped when the PR sequence has the alternating pattern “10 01”.
Described next is the case in which two or more zero crossings occur along one of the axes during signal transition due to frequency shift being included in a signal having arc-shaped transition characteristics.
FIG. 9 is a timing chart showing zero-crossing signals when phase shift is absent. As is also apparent from the FIG. 6 signal transitions, the fact that zero crossings occur within the symbol cycle long both the I/Q axes in the case of phase shift being absent means that zero-crossing signals along the I/Q axes occur at one symbol intervals with respect to the symbol clock being recovered, and thus the successive phase errors EI and EQ are respectively the same. Accordingly, these zero-crossing signals are valid phase error information.
FIG. 10 schematically shows signal transition with additive +45° phase shift and noise in the detected signal shown in FIG. 6. As shown in FIG. 10, the signal points disperse with additive noise, widening the locus of the signal transition.
FIG. 11 is a schematic diagram showing the detected signal in FIG. 10 crossing the I/Q axes. The majority of transitions AB can be classified into the following four types.Transition AB12: 1st→2nd quadrantTransition AB123: 1st→2nd→3rd quadrantTransition AB412: 4th→1st→2nd quadrantTransition AB4123: 4th→1st→2nd→3rd quadrant
FIG. 12 is a schematic diagram showing zero-crossing signals and phase errors for transition AB4123. With transition AB4123, zero-crossing signals occur along both the I/Q axes as shown in FIG. 12. Note that with phase error EI in the in-phase (I) component, at least two zero-crossing signals occur per symbol period owning to the arc-shaped signal transition.
Consider an example in which the conventional error selection circuit discussed above judges the validity of phase error information when the input signal corresponds to the PR and the detected signal alternates in sign. In the case of two zero-crossing signals occurring at regular intervals (=0.5 T, where T=1 symbol period) per symbol period, pseudo eyes occur on either side of the eye pattern originally to be captured. While the true eye needs to be specified and sampled from this signal as phase error information, clock recovery with the conventional error selection circuit is unstable because of the two zero-crossing signals per symbol period being judged valid when Tcmin is set below 0.5 T. On the other hand, phase error information is not detected when Tcmin is set above 0.5 T because of both zero-crossing signals being judged invalid, making clock recovery impossible. Thus when the conventional error selection circuit is applied in relation to an alternating pattern PR with phase shift caused by frequency shift present in the detected signal, normal clock locking operations cannot be realized.